Electronic devices are continually getting smaller, faster, and using less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal audio devices (e.g., MP3 players) are in great demand in the consumer market. Such electronic devices rely on a limited power source (e.g., batteries) while providing ever-increasing processing capabilities and storage capacity.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). These goals have been achieved in great part by scaling down the dimensions of semiconductor ICs and thus increasing device and circuit densities. Achieving higher densities calls for smaller feature sizes, smaller separations between features and layers, and more precise feature shapes. The scaling down of IC dimensions can facilitate faster circuit performance (e.g., faster switching speeds) and can lead to higher effective yield in IC fabrication processes by providing (i.e., “packing”) more circuits on a semiconductor die and/or more die on a semiconductor wafer.
A fundamental building block of semiconductor ICs is the metal-oxide semiconductor (MOS) transistor. FIG. 1 illustrates a cross-section of a MOS transistor 100. The transistor 100 is fabricated on a semiconductor substrate 110 and comprises a gate stack 120. The gate stack 120 comprises a gate dielectric 130 (e.g., silicon dioxide) and a gate electrode 140 (e.g., polysilicon) on the gate dielectric 130. The transistor 100 also comprises a source region 150 and a drain region 160 each formed within the semiconductor substrate 110. A channel 170 is defined between the source and drain regions 150, 160, under the gate dielectric 130, and within the semiconductor substrate 110. The channel 170 has an associated channel length “L” and an associated channel width “W”. When a bias voltage greater than a threshold voltage (Vt) (i.e., turn-on voltage) for the transistor 100 is applied to the gate electrode 140 along with a concurrently applied bias voltage between the source and drain regions 150, 160, an electric current (e.g., a transistor drive current) flows between the source and drain regions 150, 160 through the channel 170. The amount of drive current developed for a given bias voltage (e.g., applied to the gate electrode 140 or between the source and drain regions 150, 160) is a function of, among others, the width-to-length ratio (W/L) of the channel 170.
MOS transistors have become cheaper, faster, and less power-hungry with each new technology generation as the physical dimensions and applied voltages have been scaled down. To date, most transistor scaling has been achieved by thinning the gate dielectric 130 or reducing the channel length “L”. However, as transistor scaling moves into the nanometer-scale regime, scaling the gate dielectric 130 thickness or the channel length “L” is not sufficient as new phenomenon appear (e.g., leakage current flowing through the gate dielectric 130, polysilicon gate electrode depletion effects (“poly-depletion”), and contact resistance effects), which reduce the transistor drive current. The poly-depletion effect is characterized by a polysilicon gate electrode 140 that is no longer fully conductive and contributes an additional capacitance (in series) between the gate electrode 140 and the silicon substrate 110, resulting in reduced transistor drive current. New gate dielectrics having a high dielectric constant (“high-K” gate dielectrics) have been introduced in an effort to improve transistor drive current without increasing the leakage current through the gate dielectric 130. However, high-K gate dielectrics face reliability and compatibility issues with polysilicon gate electrodes such as poor work function control, which results in, for example, transistors having an unsuitable threshold voltage (Vt). For other gate dielectric materials such as silicon dioxide, polysilicon gate electrodes become problematic with scaling due to the poly-depletion effect and contact resistance problems.